The present invention relates to apparatuses to encode picture signals in redundancy reduction encoding system, and more particularly to a picture signal processing apparatus which is suitable for a high-speed facsimile or the like.
In a facsimile in the prior art, an encoding means which converts digital picture signals into redundancy reduction code and performs encoding processing is known well as disclosed in Nakamura et al. "Development of Signal-Chip Facsimile Codec Processor (FCP)", paper No. 1374, presented at 1984 General Meeting of the Institute of Electronics and Communication Engineers of Japan. Also a signal processing means which performs signal processing such as picture element density conversion of digital picture signals is known well as disclosed in "A CMOS Facsimile Video Signal Processor (FVP)", presented at IEEE INTERNATIONAL SOLID STATE CIRCUITS CONFERENCE. However, any system to combine such signal processing means with encoding means and to perform high-speed processing has not been thought.